1. Field of the Invention
The present invention relates to digital logic circuitry, and more specifically to built-in self test of digital logic circuitry.
2. Description of the Related Art
Testing of integrated circuits (ICs) has become vitally important in the electronics industry. Typically, ICs are tested by use of automatic test equipment (ATE) and mechanical handling equipment, which automates the testing process. The controllability of test sequences, and of conditions such as voltage and temperature, coupled with the ability to archive and analyze test results, offers great convenience in the manufacturing and test of ICs.
This approach, however, is not without its problems. ATE is generally expensive because it is complex. To maximize their ATE investment, companies want their ATE to interface to ICs of different types. This requires the development of custom interface hardware between the ATE and the IC under test. The interface hardware introduces parasitics and time delays that can have a detrimental effect on test efficiency and accuracy.
Moreover, ATE requires the development of specialized software that is specific to the IC under test. This software comprises sequences of input stimuli, sequences of corresponding output responses, and the order and conditions under which these sequences are applied to the IC under test.
Built-in self-test (BIST) is commonly practiced in the electronics industry as a means to circumvent some of these problems. By placing circuitry on chip to apply the test sequences that would otherwise be applied by the ATE, BIST provides a solution to the problems posed by test interface hardware. BIST potentially enables the testing of the chip at full operating frequencies, because the BIST circuitry is fabricated of the same technology as the circuit under test, and can be placed immediately adjacent to the circuitry under test. BIST also potentially enables an IC to be tested in situ following the integration of the IC into a system-level product, as the test algorithm resides on-chip rather than with the ATE.
Any BIST circuitry increases the area, and hence the cost, of the IC die. As a result, the degree of BIST implementation, and the increased test coverage achieved by such implementation, must be traded off against the increased die area and associated cost. The degree of test coverage achieved through BIST is a function of the die area consumed by BIST. The current economics of the IC industry require that the ratio of circuitry under test to BIST circuitry must remain relatively high. Consequently, typical BIST implementations control and observe only the primary inputs and outputs of a relatively large block of logic. Further analysis and testing must then be conducted without BIST to pinpoint BIST-identified problems.
The conventional approach of using ATE to apply test sequences that have been generated off-chip suffers from this problem to an even greater degree. This conventional approach permits control and observability only at the chip boundary, which is limited to the primary inputs and primary outputs of the chip. BIST has eased, but not solved completely, the problem of limited node access.
The problem of poor access to interior circuit nodes, encountered when using ATE to drive primary inputs and strobe primary outputs of an IC, has been commonly addressed in the industry through the implementation of a technique known as "scan access." Scan access refers broadly to the use of specialized serial shift registers ("scan registers") to deliver stimulus vectors from a stimulus pattern generator to circuit nodes of interest, and to retrieve response data from circuit nodes of interest for analysis. Scan registers function as normal synchronous registers and latch data propagating through the computational logic. However, scan registers can also be interconnected in such a way as to allow propagation of data directly from register to register upon assertion of BIST control signals or clocks, thereby bypassing any computation logic between the registers. This provides a means whereby stimulus data may be transported directly to internal circuit nodes without propagating through computational logic, and whereby response data may be retrieved directly from internal circuit nodes without propagating through computational logic, thus allowing designers to isolate sections of logic for testing. By way of illustration, consider two partitions of logic circuitry, Partition 1 and Partition 2, residing on a single hypothetical chip without scan access. Assume that the circuitry is configured such that only Partition 1 is directly accessible from primary inputs of the chip and only Partition 2 is coupled to primary outputs of the chip. Assume further that the inputs of Partition 2 are driven only by the outputs of Partition 1. To test Partition 2, designers must compute the particular stimulus vectors that, when placed on the inputs to Partition 2, exercise the faults of interest within Partition 2. However, to apply those stimulus vectors to Partition 2, designers must also map the Partition 2 stimulus vectors backwards through the logic of Partition 1 to obtain the corresponding primary inputs stimulus vectors. In many cases this mapping may be logically impossible, rendering certain faults within Partition 2 untestable. The implementation of scan access, however, would place scan registers at the boundary between Partitions 1 and 2, interconnected in such a way that stimulus vectors for Partition 2 could be serially shifted directly onto the inputs of Partition 2 without passing through Partition 1, enhancing the testability of Partition 2.
A similar benefit is realized with respect to the retrieval of response data. The implementation of scan access as described above would also enable the direct retrieval of response data from the outputs of Partition 1 without passing through Partition 2. This obviates the need to map the output response vectors of Partition 1 through the logic of Partition 2 and enhances the testability of Partition 1.
The benefit of scan access increases as the proportion of circuit nodes otherwise inaccessible from primary inputs and outputs increases. "Full scan" refers to an implementation of scan access wherein every register on a chip is accessible through scan. "Partial scan" refers to an implementation of scan access wherein some subset of the registers on a chip are accessible through scan.
Conventional scan access, i.e., propagating data through a long chain of interconnected scan registers, is inherently serial in nature. The number of clock cycles needed to load or unload the scan chain is equal to the number of registers in the chain. Gaining access to internal nodes is therefore accomplished only at the cost of very long test times. Scan access also does not relieve the burden of test software development. Stimulus and response patterns must still be computed off-chip, prior to test time.
Alternate scan architectures such as random access scan have been used to remedy the test time problem caused by the serial nature of scan access. Random access scan, mploys individually-addressable registers rather than registers connected in a fixed order. This adds greater flexibility to the order in which registers may be accessed, but reduces overall test time only when writing or reading some subset of the registers. Random access scan does not decrease the total number of clock cycles needed to write or read all registers.